This invention generally relates to semiconductor device manufacturing methods and more particularly to a method for reforming a hydrophobic low-k dielectric insulating layer surface to a hydrophilic surface for improved adhesion to adjacently formed material layers.
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multi-level semiconductor device. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been signal delay caused by parasitic effects of insulating materials in which metal interconnects are formed to interconnect devices. It has become necessary to reduce capacitance of the insulating layers to allow the insulating layer thicknesses to shrink along with other device features such as metal interconnect line width. As a result, the need for lower dielectric constant materials has resulted in the development of several different types of organic and inorganic low-k materials.
During the formation of semiconductor devices it is often required that the conductive layers be interconnected through holes in an insulating layer. Such holes are commonly referred to as contact holes when the hole extends through an insulating layer to an active device area, or vias, when the hole extends through an insulating layer between two conductive layers.
Manufacturing processes such as, for example, damascene processes, have been implemented to form metallization vias and interconnect lines (trench lines) by dispensing entirely with the metal etching process. The damascene process is a well known semiconductor fabrication method for forming multiple layers of metallization vias and interconnect lines. For example, in the dual damascene process, a trench opening and via opening is etched in one or more dielectric insulating layers also known as an inter-metal dielectric (IMD) layers or inter-level dielectric (ILD) layers. The insulating layers are typically formed over a substrate including another conductive area over which the vias and trench lines are formed to provide electrical communication. After a series of photolithographic steps defining via openings and trench openings, via and the trench openings are filled with a metal, preferably copper, to form vias and trench lines, respectively. The excess metal above the trench line level is then removed by well known chemical-mechanical planarization (polishing) (CMP) processes.
As indicated, advances in semiconductor device processing technology demands the increasing use of low-k (low dielectric constant) insulating materials in, for example, inter-metal dielectric (IMD) layers that make up the bulk of a multi-level device. In order to reduce signal delays caused by parasitic effects related to the capacitance of insulating layers, for example, IMD layers, incorporation of low-k materials with dielectric constants less than about 3.5 has become standard practice as semiconductor feature sizes have diminished to 0.13 microns and below. Many of the low-k materials are designed with a high degree of porosity to allow the achievement of lower dielectric constants. Several silicon oxide based materials have been developed including fluorine doped and hydrocarbon doped silicon oxides also often referred to as organo silicate glass (OSG) formed in layers, for example IMD layers, by CVD or spin-on processes where the dielectric constant may be varied over a range of values depending on the precursors and process conditions. Low-k doped silicon oxides for example, may be formed with dielectric constants over a range of about 1.8 to about 3.2 and having densities of about 1.3 g/cm3 to about 1.8 g/cm3 compared to dielectric constants of about 4.1 and a density of about 2.3 g/cm3 for silicon dioxides (e.g., un-doped TEOS).
Among the problems presented by doped silicon oxide low-k materials including IMD layers are low strength and a proclivity to cracking or peeling in subsequent stress-inducing manufacturing processes including, for example, chemical mechanical planarization (CMP). The problem of peeling is related to the poor adhesion demonstrated by typical low-k IMD layers to deposited overlying layers, thereby peeling when stresses oriented parallel to the layer interfaces are applied, for example in CMP processes. Several approaches in the prior art to solve the peeling problem have included adding one or more capping layers over the low-k dielectric insulating layers including, for example, silicon dioxide (e.g., CVD TEOS), or spin-on glasses (SOG). While capping layers have had some success, the addition of the capping layers contributes undesirably to the overall capacitance of the multi-level device. In addition, the capping layers have themselves often demonstrate poor adhesion to overlying layers.
It would therefore be advantageous to develop a method for forming a low-k dielectric insulating layer with improved layer interface adhesion while reducing contributions to overall capacitance in a multi-layer semiconductor device.
It is therefore an object of the invention to provide a method for forming a low-k dielectric insulating layer with improved layer-interface adhesion while reducing contributions to overall capacitance in a multi-layer semiconductor device while overcoming other deficiencies and shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming a dielectric insulating layer with increased hydrophilicity for improving adhesion of an adjacently deposited material layer in semiconductor device manufacturing.
In a first embodiment, the method includes providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing the dielectric insulating layer; and, subjecting the dielectric insulating layer including an exposed surface to a hydrophilicity increasing treatment including at least one of a dry plasma treatment and a wet process including contacting the exposed surface with a
hydrophilicity increasing solution including a surfactant said wet process followed by a baking process to improve an adhesion of an adjacently deposited material layer.